Session Description: SoC Top Level Analog Verification using Cadence AMS
Cristian M Albina, Ganesan Iyer, Divakar Sura
Microchip Technology Inc., 2355 W Chandler Blvd, Chandler, AZ. 85224, USA
Top level simulations are very time consuming due to the complexity of the integrated circuits and the high number of transistors. Debugging the analog issues using the top level SoC schematic is easier than navigating through the large netlist. Using the Cadence Verilog-In command we can import the top level RTL synthesized netlist generated by the top level design team. During the early design phase using several sub-system simulation test benches we are able to verify the analog functionality, trace the inter-blocks connectivity and identify design issues of the analog modules, all of which are harder to do at the top level. Using the vectors generated by the digital top level simulation as an input for the analog sub-system we can compare the results of the analog and digital simulations to ensure the correct functionality and run a full power report analysis. Creating a top level test bench we can run whole chip AMS simulation in order to debug DC problems and HiZ paths, verify the chip power-up and power-down modes and identify integration issues at the analog-digital interfaces. The Cadence AMS simulation environment allows us to setup and run all these tests. Additionally by using a combination of schematic and behavioral models we can reduce the simulation time significantly. Furthermore starting the simulation in batch command line mode combined with multi-core and multi-thread options we can achieve up to 40-50% run time reduction. Having a high quality verification process allows us to insure the functional success of the silicon and reduce the costly re-design steps.
Cristian Albina Bio: Cristian Albina is the Analog Development Manager for the Wireless Solutions Group (WSG) in Microchip's Chandler, Arizona headquarters and IEEE Senior Member. He has been working in the semiconductor industry for more than 20 years in the areas of analog and high-frequency design. Cristian's role extends from transistor level, mixed-signal design and layout through implementation of custom design flows, design porting across
different technologies and EDA tools support.
He received his B.Sc. /M.Sc. EE and Ph.D. EE Degrees from “POLITEHNICA” University in Bucharest.