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Session Track: Custom / Advanced Node
CUS101 (Texas Instruments ) Virtuoso ADE Verifier in Real-Life Environment
  • Speaker: Christian Harder, Analog Design Engineer, Texas Instruments
    Josy Bernard 
Time: Tuesday, April 11, 9:30am - 10:10am , Room: Room 201
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Session Description: Increasing analog design complexity requires well planned and managed verification approaches to integrate analog regression and self-checking tests into the analog design engineer’s work flow. This still requires extensive use of additional tools and hand-crafted scripts that only manually integrate into the existing analog design environment such as Cadence ADE L. So far there was no standardized methodology to set up the features described above. ADE XL, introducing specification checks, made a first step towards analog verification, but was in general not flexible enough to provide all the features needed. Cadence Assembler, the successor of ADE XL, integrates seamlessly into Cadence Verifier, a new GUI based analog verification suite.

Christian Harder Bio: Christian Harder received his Master in Electrical Engineering with focus on integrated analog circuits in 2014 from RWTH Aachen University. Since then he is with Texas Instruments as analog design engineer working on switch mode converters and auxiliary circuits for display bias ICs.
Josy Bernard Bio: Josy Bernard joined TI-Freising in 2009 and is currently Digital Design Manager leading a verification team and a digital design team. He is holding a master's degree in electrical engineering of the RWTH Aachen University, Germany. Josy is lead designer of several power management ICs and display specific high voltage level shifters. His current focus is to bring modern verification techniques to the power management world and drive the digital integration of these devices.
Session Track: Front-End Design
FED101 (Texas Instruments) LBIST Implementation in the Context of Automotive Safety
  • Speaker: George Konnail, Digital Design Manager, Texas Instruments
    Arvind Chokhani
    Abdel Alsharqawi 
Time: Tuesday, April 11, 9:30am - 10:10am , Room: Room 203
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Session Description: Use of semiconductor chips in automotive applications has been growing at an exponential rate. The critical functions performed by these chips has led to tougher automotive standards such as ISO26262 covering the product lifecycle from specification, design, through verification and validation. Functional safety applications often stipulate the need for logic built in self-test (LBIST) to be run periodically to look for random failures that could show up in the field rather than during production tests. Even power ON tests cannot sometimes guarantee reliability in the extreme conditions which could change from the controlled environment in a garage to the -20 degree Fahrenheit or 120 degree Fahrenheit on the road. This requirement presents unique challenges in terms of being able to run critical tests in mission mode by suspending normal application to run LBIST and to recover from LBIST back to normal operation after LBIST is run. There is also sometimes a need to run LBIST on a subset of the digital logic during low power mode. This paper presents one approach to address these challenges.

George Konnail Bio: George Konnail is a Digital Design Manager at Texas Instruments. His team focuses on mixed signal ICs for automotive and functional safety applications. He has 20 years of experience in the semiconductor industry. He holds a MS/EE from Southern Illinois University
Arvind Chokhani Bio: Arvind Chokhani is Staff Application Engineer at Cadence Design Systems and based out of Dallas. He did his Masters of Science in Electrical Engineering from University of Cincinnati in 2003. He has previously worked at Texas Instruments, Freescale and NXP as Design for Test Engineer.
Abdel Alsharqawi Bio: Abdel Alsharqawi is a Digital Design Engineer at Texas Instruments; he has PhD in computer engineering from University of Central Florida in 2005. As part of his current role at Texas Instruments he is working on Safety Power Management Devices for Automotive applications.
Session Track: Digital Implementation / Advanced Node
FFA101 (Brocade) Solving Design Challenges in Macro Intensive Networking Designs Using Innovus Flow
  • Speaker: Krish Ramachandran, Physical Design Lead, Brocade 
Time: Tuesday, April 11, 9:30am - 10:10am , Room: Room 207
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Session Description: Most of Brocade’s designs are macro intensive networking designs where 70 – 80% area is occupied by memory macros, which increases the complexity for solving timing and congestion issues.. This paper discusses the challenges,, and how innovative floorplanning and placement techniques in Innovus helped these "macro intensive" designs to achieve the desirable QoR without compromising aggressive Tape-Out schedules .

Krish Ramachandran Bio: Krish is a Technical leader at Brocade communications, San Jose -where he is one of the key members in PD team for designing complex networking ASICs. Prior to joining Brocade, Krish worked at Oracle where he was an Integration lead for designing high speed SPARC processors. Krish has over 20 years of industrial experience. Krish received B.S.E.E in India and M.S.E.E from San Jose State University.
Session Track: IP / Block Verification
IPB101 (Cadence) The Cadence Verification Suite – Faster, Smarter Verification
  • Speaker: Frank Schirrmeister 
Time: Tuesday, April 11, 9:30am - 10:10am , Room: Room 209
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Session Description: As a combination of best in class engines for formal verification, simulation, emulation and FPGA based prototyping with a verification fabric offering verification management, debug, verification IP and portable stimulus for software driven SoC verification, the Cadence Verification Suite greatly accelerates time to market. This presentation will update on the latest improvements in the Verification Suite with a special focus on efficient integration of the engines, and will put the presentations in the two verification related CDNLive tracks in perspective. We will also provide and update on the latest trends driving the future of verification.

Frank Schirrmeister Bio:
Session Track: Mixed-Signal Design
MIX101 (Microchip Technology) SoC Top-Level Analog Verification Using Cadence AMS
  • Speaker: Cristian Albina, Analog Development Manager, Microchip Technology Inc. 
Time: Tuesday, April 11, 9:30am - 10:10am , Room: Room 206
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Session Description: SoC Top Level Analog Verification using Cadence AMS Cristian M Albina, Ganesan Iyer, Divakar Sura Microchip Technology Inc., 2355 W Chandler Blvd, Chandler, AZ. 85224, USA Abstract Top level simulations are very time consuming due to the complexity of the integrated circuits and the high number of transistors. Debugging the analog issues using the top level SoC schematic is easier than navigating through the large netlist. Using the Cadence Verilog-In command we can import the top level RTL synthesized netlist generated by the top level design team. During the early design phase using several sub-system simulation test benches we are able to verify the analog functionality, trace the inter-blocks connectivity and identify design issues of the analog modules, all of which are harder to do at the top level. Using the vectors generated by the digital top level simulation as an input for the analog sub-system we can compare the results of the analog and digital simulations to ensure the correct functionality and run a full power report analysis. Creating a top level test bench we can run whole chip AMS simulation in order to debug DC problems and HiZ paths, verify the chip power-up and power-down modes and identify integration issues at the analog-digital interfaces. The Cadence AMS simulation environment allows us to setup and run all these tests. Additionally by using a combination of schematic and behavioral models we can reduce the simulation time significantly. Furthermore starting the simulation in batch command line mode combined with multi-core and multi-thread options we can achieve up to 40-50% run time reduction. Having a high quality verification process allows us to insure the functional success of the silicon and reduce the costly re-design steps.

Cristian Albina Bio: Cristian Albina is the Analog Development Manager for the Wireless Solutions Group (WSG) in Microchip's Chandler, Arizona headquarters and IEEE Senior Member. He has been working in the semiconductor industry for more than 20 years in the areas of analog and high-frequency design. Cristian's role extends from transistor level, mixed-signal design and layout through implementation of custom design flows, design porting across different technologies and EDA tools support. He received his B.Sc. /M.Sc. EE and Ph.D. EE Degrees from “POLITEHNICA” University in Bucharest.
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